Some months ago, there was a brief discussion of the pipelining used in some of the new "one-clockers" that boast realy high speed.

Earlier today, I was told about about a problem with the pipeline in the SiLabs 100-MIPS MCU's that made it work OK with up to eight (?) instructions in a loop but let it fall apart, meaning the critical timing of the loop "broke" when there were more than eight bytes in the loop.

I've been considering using one of the MCU's in this series but can't find enough in the datasheet about the pipeline. That would affect not only the timing of long loops, but also the interrupt response time.

Does anyone have precise and detailed information about this?

I need to know how the pipeline will affect loops with 300+ instructions per loop.

I've noted that the Dallas Semiconductor design used in their Maxim/Dallas DS89C4x0 series, (the '420 and '440 of which are being discontinued, according to their support person) has no such pipelining, though they do indicate they use a 4-stage pipeline, as did the original 805x (I'm not sure about that, but I do seem to recall that figure). This implies that the Dallas parts will execute a long loop faster than the SiLabs parts, despite the fact that the SiLabs parts claims a 10 ns cycle while the Maxim/Dallas parts top out with a 30 ns cycle.

This is heavily dependent on the loop length, however, and that's why I want the precise details.

Any URL's, bits of wisdom?

RE