That pipeline contains code-space memory, in sequence of execution. If a loop fits within the pipeline, then it executes at full speed. If not, i.e. if it is longer than the pipeline, then every time the pipeline depth is exceeded it must be reloaded. How long this takes is a mystery and one really can't expect the manufacturer to make this known.

Since there's no information published about just how this is implemented in the SiLabs MCU's, it's worth wondering just how close they come to the claimed performance, as compared, say, with the Maxim/Dallas parts, which are also relatively quick one-clockers, but which implement no instruciton pipelining beyond the standard. Now, Maxim has released no information about how they've worked their "4-level pipeline" either. However, their MCU continues to run at the same rate without regard for the length the current loop.

I'm having to produce some precisely timed code, the behavior of which, with respect to some external hardware, must be entirely predictable.

In light of recently acquired information about the behavior of the SiLabs pipeline in at least one application makes me worry that I won't be able to exploit the full perforance of the MCU because it only runs at full speed when entirely inside the pipeline. How the thing performs when repeatedly executing a long loop is a critical thing to know. I'm hoping someone already knows this.

RE