??? 11/03/06 01:21 Read: times |
#127292 - You've got it! That's the problem, for sure. Responding to: ???'s previous message |
The complaint I learned about only today, specifically targeted at the SiLabs ...F12x series that purports to run at 100 MIPS, was that a straightlined bit of code completely fell out of synchronization with its target hardware when the loop it used was doubled in length in order to compensate in timing for the extra cycle needed to take the branch.
Apparently this particular architecture relies on that pipeline and, as one would expect, suffers badly when a critically timed loop exceeds the pipeline length. Unfortunately, I haven't been able to find a spec on the pipeline depth, and that should be documented. Does anybody know how to cope with this apparently fatal problem? It essentially renders the part(s) useless, since one can't precisely time a firmware loop to synchronize with external hardware without knowing exactly (2) the pipeline depth, and (2) the reload time. RE |