??? 11/03/06 15:56 Read: times |
#127325 - They're two different things. Responding to: ???'s previous message |
A pipeline in the processor allows higher clock frequencies by processing instructions in several steps. They're like having a 12-clocker, but instead of having only one instruction move through the "12-clock" pipeline, have 12 instructions, one in each stage.
Pipelines cause their own set of problems (pipeline conflicts, i.e. if one instruction changes value X in stage 5 and another instruction, while still in the pipeline, tries to read the same value. I've had my share of this while writing firmware for a TI TMS320VC5407, and its pipeline is only 6 stages), and they're a real liability when the program branches. In that case, the processor might have to flush and re-fill the pipeline if it didn't guess right whether the code branches or not. Some processors will always guess one way (for example "doesn't branch"), but this might result in very sub-optimal behavior (imagine a loop that runs X times - the guess is wrong X times and right once), but is very predictable. If a processor tries to guess if the code will branch or not, or (as the SiLabs part does) keeps the pipeline contents for both possibilities in a cache, the code will run a lot faster, but it will also become very unpredictable (depending on previously executed code, etc). |