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???
11/03/06 15:56
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#127325 - They're two different things.
Responding to: ???'s previous message
A pipeline in the processor allows higher clock frequencies by processing instructions in several steps. They're like having a 12-clocker, but instead of having only one instruction move through the "12-clock" pipeline, have 12 instructions, one in each stage.

Pipelines cause their own set of problems (pipeline conflicts, i.e. if one instruction changes value X in stage 5 and another instruction, while still in the pipeline, tries to read the same value. I've had my share of this while writing firmware for a TI TMS320VC5407, and its pipeline is only 6 stages), and they're a real liability when the program branches. In that case, the processor might have to flush and re-fill the pipeline if it didn't guess right whether the code branches or not. Some processors will always guess one way (for example "doesn't branch"), but this might result in very sub-optimal behavior (imagine a loop that runs X times - the guess is wrong X times and right once), but is very predictable.

If a processor tries to guess if the code will branch or not, or (as the SiLabs part does) keeps the pipeline contents for both possibilities in a cache, the code will run a lot faster, but it will also become very unpredictable (depending on previously executed code, etc).



List of 33 messages in thread
TopicAuthorDate
Pipelines revisited            01/01/70 00:00      
   You cannot say without more information            01/01/70 00:00      
      You've got it! That's the problem, for sure.            01/01/70 00:00      
         Synchronization            01/01/70 00:00      
            True enough, but in this case            01/01/70 00:00      
   So you can be happily chugging away            01/01/70 00:00      
      That renders the SiLabs architecture unuseable            01/01/70 00:00      
         Can't You Trurn it off?            01/01/70 00:00      
         Advertising.            01/01/70 00:00      
            a better term would have been "unspecified"            01/01/70 00:00      
         if what you want is to bitch, the cache stinks, if            01/01/70 00:00      
            No ... it's not just a complaint ...            01/01/70 00:00      
               experience and the other is stated already            01/01/70 00:00      
                  it's not quite that simple ...            01/01/70 00:00      
                     does not matter, in this case an advantage            01/01/70 00:00      
                        Yes, same length, irrespective of path            01/01/70 00:00      
   can you explain more?            01/01/70 00:00      
      It uses a pipeline to achieve the high speed            01/01/70 00:00      
         why pipeline??            01/01/70 00:00      
   branch cache            01/01/70 00:00      
      i dont know about slightly unpredictable            01/01/70 00:00      
      I second this.            01/01/70 00:00      
      It's called "branche cache" rather than pipeline?            01/01/70 00:00      
         They're two different things.            01/01/70 00:00      
            This flush and refill process is what I feared            01/01/70 00:00      
         you might also try something completely different            01/01/70 00:00      
            well ... maybe ...            01/01/70 00:00      
   what is the problem?            01/01/70 00:00      
      The problem is blaming the pipeline ...            01/01/70 00:00      
         oh, I wish            01/01/70 00:00      
         Exactly ...            01/01/70 00:00      
      That reference is helpful            01/01/70 00:00      
         not a "litterary masterpiece" but after reading            01/01/70 00:00      

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