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???
11/03/06 15:40
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#127323 - It's called "branche cache" rather than pipeline?
Responding to: ???'s previous message
I've only been "on" this task since yesterday, and have had to deal with both the "newness" of this information, at least to me, and also the not-too-clear explanation of the problem from my colleague. That's why I asked the question here, since there are a few users who've already encountered this information, hence, have knowledge of (1) where it is documented, and (2) what its impact is.

What I have to do is to demodulate an encoded stream of data being sampled in the Mode 0 serial channel. Each bit is represented by what amounts to a two-bit symbol. Each bit is sampled four times. A table-lookup is one way in which a symbol, so encoded and oversampled, can be translated. The lookup table is a 256-entry table, hence, the content of A can ideally serve as an index. However, the decision as to the table is made on the basis of a flag which is residue from the result obtained from the previous byte. Additionally, there are occasional (very rare, relative to the bit rate) timing corrections that have to be made due to slight variations in the data rate due to difference between the crystals used in the MCU and the data source. There are also other variations in rate that require this timing adjustment.

All this has to be accomodated in the code. The key is predictability of the MCU's execution. The presence of a cache, pipeline, prefetch queue, or whatever, doesn't matter, so long as it's characterized correctly. Once that's done, it's entirely predictable, if not jitter-free.

Is this information in the datasheet or in the User Guide? Both? I spent some time searching in Acrobat Reader, just to get a "feel" for this feature (I didn't get one!), but haven't yet sat down and read the doc's yet. I'm still trying to assess whether this part can do the job "better" or more easily than the somewhat slower Maxim/Dallas part.

RE




List of 33 messages in thread
TopicAuthorDate
Pipelines revisited            01/01/70 00:00      
   You cannot say without more information            01/01/70 00:00      
      You've got it! That's the problem, for sure.            01/01/70 00:00      
         Synchronization            01/01/70 00:00      
            True enough, but in this case            01/01/70 00:00      
   So you can be happily chugging away            01/01/70 00:00      
      That renders the SiLabs architecture unuseable            01/01/70 00:00      
         Can't You Trurn it off?            01/01/70 00:00      
         Advertising.            01/01/70 00:00      
            a better term would have been "unspecified"            01/01/70 00:00      
         if what you want is to bitch, the cache stinks, if            01/01/70 00:00      
            No ... it's not just a complaint ...            01/01/70 00:00      
               experience and the other is stated already            01/01/70 00:00      
                  it's not quite that simple ...            01/01/70 00:00      
                     does not matter, in this case an advantage            01/01/70 00:00      
                        Yes, same length, irrespective of path            01/01/70 00:00      
   can you explain more?            01/01/70 00:00      
      It uses a pipeline to achieve the high speed            01/01/70 00:00      
         why pipeline??            01/01/70 00:00      
   branch cache            01/01/70 00:00      
      i dont know about slightly unpredictable            01/01/70 00:00      
      I second this.            01/01/70 00:00      
      It's called "branche cache" rather than pipeline?            01/01/70 00:00      
         They're two different things.            01/01/70 00:00      
            This flush and refill process is what I feared            01/01/70 00:00      
         you might also try something completely different            01/01/70 00:00      
            well ... maybe ...            01/01/70 00:00      
   what is the problem?            01/01/70 00:00      
      The problem is blaming the pipeline ...            01/01/70 00:00      
         oh, I wish            01/01/70 00:00      
         Exactly ...            01/01/70 00:00      
      That reference is helpful            01/01/70 00:00      
         not a "litterary masterpiece" but after reading            01/01/70 00:00      

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