| ??? 11/03/06 11:35 Modified: 11/03/06 11:36 Read: times |
#127311 - why pipeline?? Responding to: ???'s previous message |
hi,
Richard Erlacher said:
That pipeline contains code-space memory, in sequence of execution. If a loop fits within the pipeline, then it executes at full speed.
Which loop do you talk about? SiLabs F12x/13x executes a program at full speed as long as the code execution is linear (this is the task of prefetch engine) or if it presents in the cache as well. If not, i.e. if it is longer than the pipeline, then every time the pipeline depth is exceeded it must be reloaded.
I think we talk about different things. SiLabs has nor "pipeline depth" neither "pipeline reload". They use prefetch engine and branch target cache -- that`s all. How long this takes is a mystery and one really can't expect the manufacturer to make this known.
All the timings of each instruction are indicated in the chapter "Instruction Set". Cache-miss penalty duration is defined and explained in the chapter "Branch Targed Cache". Since there's no information published about just how this is implemented in the SiLabs MCU's, it's worth wondering just how close they come to the claimed performance, as compared, say, with the Maxim/Dallas parts, which are also relatively quick one-clockers, but which implement no instruciton pipelining beyond the standard. Now, Maxim has released no information about how they've worked their "4-level pipeline" either. However, their MCU continues to run at the same rate without regard for the length the current loop.
Read above about SiLabs: "When running linear code (code without any jumps or branches), the prefetch engine alone allows instructions to be executed at full speed." Regards, Oleg |
