| ??? 11/03/06 08:13 Read: times Msg Score: +1 +1 Good Answer/Helpful |
#127306 - branch cache Responding to: ???'s previous message |
There are 2 things confused here, I believe: the pipeline of the processor core itself, and the prefetch mechanism which supplies the code for the core at the required pace.
Mind, the FLASH access time is 40ns, whereas the core needs to be supplied a code byte each 10ns... Clearly, there must be some sort of parallelism in reading the FLASH and a buffering between the FLASH and the core, which in effect works as a prefetch queue. This prefetch gets flushed of course at jumps, resulting in stalls. At SiLabs, they went further, and to prevent stalls at branches they implemented branch cache. Although this makes the timing slightly unpredictible especially when interrupts are involved; there are mechanisms to lock the content of cache or to switch it off completely, to cope with this. You (or your friends) might want to read the chapter on branch cache in the datasheet, it is very interesting, even if not giving an absolutely complete information. Jan Waclawek |
