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???
11/03/06 16:10
Modified:
  11/03/06 16:16
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 		 #127330 - experience and the other is stated already
Responding to: ???'s previous message
What is the basis for your comment about the 85 MIPS rate?
experience, my stuff run in that neighborhood
Can you direct me to any documentation that supports the sort of function I want to create?
assuming you refer to the "small precisely timed loop": stated already http://www.8052.com/forum/read.phtml?id=127313 chapter 16 in the datasheet. Playing with the cahche is "real fun" but once you get the drift of it quite easy.

one more comment:
if the time is 'irrelevant' but the precision of the time is 'relevant' the simple solution is to make the linker save the particular routine at the same place every time. The only way the timing of a routine is 'unpredictable' is when the linker keep relocating it. ANY routine in ANY location will (save for interrupts, of course) ALWAYS execute in the same time till it is changed or relocated.

Erik


List of 33 messages in thread
TopicAuthorDate
Pipelines revisited            01/01/70 00:00      
   You cannot say without more information            01/01/70 00:00      
      You've got it! That's the problem, for sure.            01/01/70 00:00      
         Synchronization            01/01/70 00:00      
            True enough, but in this case            01/01/70 00:00      
   So you can be happily chugging away            01/01/70 00:00      
      That renders the SiLabs architecture unuseable            01/01/70 00:00      
         Can't You Trurn it off?            01/01/70 00:00      
         Advertising.            01/01/70 00:00      
            a better term would have been "unspecified"            01/01/70 00:00      
         if what you want is to bitch, the cache stinks, if            01/01/70 00:00      
            No ... it's not just a complaint ...            01/01/70 00:00      
               experience and the other is stated already            01/01/70 00:00      
                  it's not quite that simple ...            01/01/70 00:00      
                     does not matter, in this case an advantage            01/01/70 00:00      
                        Yes, same length, irrespective of path            01/01/70 00:00      
   can you explain more?            01/01/70 00:00      
      It uses a pipeline to achieve the high speed            01/01/70 00:00      
         why pipeline??            01/01/70 00:00      
   branch cache            01/01/70 00:00      
      i dont know about slightly unpredictable            01/01/70 00:00      
      I second this.            01/01/70 00:00      
      It's called "branche cache" rather than pipeline?            01/01/70 00:00      
         They're two different things.            01/01/70 00:00      
            This flush and refill process is what I feared            01/01/70 00:00      
         you might also try something completely different            01/01/70 00:00      
            well ... maybe ...            01/01/70 00:00      
   what is the problem?            01/01/70 00:00      
      The problem is blaming the pipeline ...            01/01/70 00:00      
         oh, I wish            01/01/70 00:00      
         Exactly ...            01/01/70 00:00      
      That reference is helpful            01/01/70 00:00      
         not a "litterary masterpiece" but after reading            01/01/70 00:00      

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