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???
11/03/06 10:20
Modified:
  11/03/06 10:23

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#127310 - Synchronization
Responding to: ???'s previous message
It essentially renders the part(s) useless, since one can't precisely time a firmware loop

Well, if you really want to count cycles to achieve synchronization, then any part with caching might be useless for your application.

I'm having some major headaches here with this concept due to a communication protocol that was once designed to be handled by 16 MHz 12-clockers, and now handles a number of different devices with wildly different clock frequencies and architectures.

I would rather design the system by taking the maximum execution time into account, and be able to deal with faster execution times. There are other methods of synchronization (external signals, timers, etc) that do not rely on a loop taking exactly the same amount of time every time, as long as a maximum (worst case) execution time is not exceeded.

List of 33 messages in thread
TopicAuthorDate
Pipelines revisited            01/01/70 00:00      
   You cannot say without more information            01/01/70 00:00      
      You've got it! That's the problem, for sure.            01/01/70 00:00      
         Synchronization            01/01/70 00:00      
            True enough, but in this case            01/01/70 00:00      
   So you can be happily chugging away            01/01/70 00:00      
      That renders the SiLabs architecture unuseable            01/01/70 00:00      
         Can't You Trurn it off?            01/01/70 00:00      
         Advertising.            01/01/70 00:00      
            a better term would have been "unspecified"            01/01/70 00:00      
         if what you want is to bitch, the cache stinks, if            01/01/70 00:00      
            No ... it's not just a complaint ...            01/01/70 00:00      
               experience and the other is stated already            01/01/70 00:00      
                  it's not quite that simple ...            01/01/70 00:00      
                     does not matter, in this case an advantage            01/01/70 00:00      
                        Yes, same length, irrespective of path            01/01/70 00:00      
   can you explain more?            01/01/70 00:00      
      It uses a pipeline to achieve the high speed            01/01/70 00:00      
         why pipeline??            01/01/70 00:00      
   branch cache            01/01/70 00:00      
      i dont know about slightly unpredictable            01/01/70 00:00      
      I second this.            01/01/70 00:00      
      It's called "branche cache" rather than pipeline?            01/01/70 00:00      
         They're two different things.            01/01/70 00:00      
            This flush and refill process is what I feared            01/01/70 00:00      
         you might also try something completely different            01/01/70 00:00      
            well ... maybe ...            01/01/70 00:00      
   what is the problem?            01/01/70 00:00      
      The problem is blaming the pipeline ...            01/01/70 00:00      
         oh, I wish            01/01/70 00:00      
         Exactly ...            01/01/70 00:00      
      That reference is helpful            01/01/70 00:00      
         not a "litterary masterpiece" but after reading            01/01/70 00:00      

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