| ??? 11/03/06 07:29 Read: times |
#127302 - can you explain more? Responding to: ???'s previous message |
hi,
I cannot understand the problem in details, sorry. Could you explain more, please? Richard Erlacher said:
Earlier today, I was told about about a problem with the pipeline in the SiLabs 100-MIPS MCU's that made it work OK with up to eight (?) instructions in a loop but let it fall apart, meaning the critical timing of the loop "broke" when there were more than eight bytes in the loop.
Which loop? What does mean "broke"? Does anyone have precise and detailed information about this?
About what? Datasheet of F12x/13x says: "Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction." Then it has indicated number of clock cycles for each instruction in the chapter "Instruction Set". I need to know how the pipeline will affect loops with 300+ instructions per loop.
Why do you repeat this word - "pipeline"? Okay, from this point of view, the pipeline is just a part of hardware which executes each instruction in time indicated in that table exactly. What you talk about? Do you think that INC A takes not 1 cycle but 2 sometimes? It essentially renders the part(s) useless, since one can't precisely time a firmware loop to synchronize with external hardware without knowing exactly (2) the pipeline depth, and (2) the reload time
If you talk about branch cache (not pipeline!) then you are able: 1) fill it with code and lock; 2) disable in the whole. Read chapter "Branch Targed Chache" to understand cache orgranization, max. number of slots etc. I think the next part says some: "When running linear code (code without any jumps or branches), the prefetch engine alone allows instructions to be executed at full speed. When a code branch occurs, a search is performed for the branch target (destination address) in the cache. If the branch target information is found in the cache (called a “cache hit”), the instruction data is read from the cache and immediately returned to the CIP-51 with no delay in code execution. If the branch target is not found in the cache (called a “cache miss”), the processor may be stalled for up to four clock cycles while the next set of four instructions is retrieved from Flash memory." May it be that there is another trouble presents in your "a firmware loop to synchronize with external hardware"? For example, it happens that people forget next note: "Note that at clock rates above 50 MHz, when a pin is written and then immediately read (i.e. a write instruction followed immediately by a read instruction), the propagation delay of the port drivers may cause the read instruction to return the previous logic level of the pin." Just as example. Regards, Oleg |
