??? 11/03/06 01:26 Read: times |
#127293 - That renders the SiLabs architecture unuseable Responding to: ???'s previous message |
If they pipeline the architecture such that if you branch out of a loop and into another it takes an indeterminate period of time to reload the pipeline, or, for that matter, to do ANYTHING AT ALL, you can't do any precise software timing with it, other than, perhaps, the simplest most brainless stuff, namely counting push-pop cycles or the like. You certaninly can't do useful work, all the while remaining in sync with a process you're controlling.
How'd they manage to sell that? This clearly makes their claim of "100 MIPS" false, except for loops shorter than whatever the pipeline is. RE |