One of the many features that this chip offers is the 2x/4x multiplier on the clock. I suspect that's what Jan is referring to in his remark about a PLL.

The internal 1KB of XRAM is located at 0x000-0x3FF by default. The User Guide (not the "bible," but "Codex Dallas/Maximus") indicates that you must explicitly set the DME0 bit (PMR.0) in order to enable the internal XRAM. This bit is always cleared on reset. Once you've done that, all accesses to XDATA within this range will be directed to the internal XRAM block. XRAM accesses outside this region will be directed to the expanded bus.

While I've used the '420 for years, I've not used the internal XRAM, nor have I used the internal ROM space, so I've not verified this. One of these days ...

Be sure you read all the errata sheets, etc, BTW.

RE