| ??? 06/20/07 07:55 Read: times |
#141069 - chips Responding to: ???'s previous message |
Matt Luckman said:
I'm not working specifically on that project, so I'd rather not say at this stage - one probable example would be chips from Silicon Labs that have on-chip debugging facilities. In addition, HI-TIDE will include a simulator for generic 8051 cores. Oh I see. Thanks. Maybe it would be nice to see more chips supported (maybe later), both in the simulator (most of the modern derivatives have different timing from the "vanilla" standard and a new simulator might want to reflect this, besides the added peripherals), and also the debugger cooperating with the on-chip debuggers on some of the derivatives. There are several commonly available '51 derivatives which do have on-chip debug facilities, besides SiLabs also the AD ADuC8xx, STM uPSD3xxxs and the Ramtron Versas (and most probably some of the NXP LPC9xx's too, but I don't know too much about those). The choice of "depth" of optimisation might then be dependent on the features those built-in tools might have (or not have). I can imagine a set of chip-specific optimiser settings, to balance between optimal code and "debuggability" on that particular chip. As Erik mentioned, there are also manufacturers of '51 emulators, with whom your company might want to cooperate. I am eagerly awaiting the news... :-) JW |
