Okay Everybody,

Many of you are bouncing right into the answer to this problem. Erik was first, and closest, when he said



And Bert Van Den Berg got close too when he brought up rise times. So with apologies to Michael, and without further adieu, ...

Here's the how and why now.

When working with high speed circuits, or digital circuits, don't think clock frequency as the speed of the circuit. Think of dv/dt (change in voltage per unit time) as the speed of the circuit. Whether you have a 1 MHz clock or a 100 MHz clock, while the signal is high it's a dc signal. When it's low it's a dc signal. It's only a time varying signal when it's changing from one state to the other. For the purposes of this discussion we will neglect ringing by pretending that we have an ideal and infinitely rigid signal.

Now think about this. When a current flows through a conductor, the speed of the electrons is not very fast. Typically, you walk faster than the electrons move. But the voltage you apply to a circuit propogates at essentially the speed of light (slightly less depending on dielectric constant). Of course, even at the speed of light, the voltage will require a finite amount of time to propogate the distance of the conductor. For purposes of this discussion, assume about 8 inches per nanosecond.

This gives rise to the idea of a critical trace length, which is the distance a signal will propogate in the time it takes to transition. It doesn't matter if you're running a 1 MHz signal or a 100 MHz signal. What matters is the transition time of the signal. Okay, at 100 MHz your total period is only what, 10 ns, so it will require a much faster transition time than a 1 MHz signal. But it's the transition time, not the clock frequency, that determines the critical trace length. If you have a 100 MHz clock with a 1 ns signal transition time, and a 1 MHz clock with a 1 ns signal transition time, then both cases will have the same critical trace length and will produce the same high speed effects. If the signal is propogating at 8 inches per nanosecond, you really need to start at least thinking about high speed effects at trace lenghts of about 4 to 6 inches.

Here's what happens. We have signals propogating at 8 inches per ns. Now suppose we have a trace that's 4 inches long. When the signal from the driver on the node goes high, it takes 1 ns, and it only takes half that time for the signal to propogate to the other end of the trace. In this case the signal appears, for all practical purposes, instantaenously. But if that same trace were 16 inches long, then for 1 ns, the signal at the driver end of the node would be high and at the other end of the same trace it would be low. Don't just read over this. Think about what was just said. For a period of time, in the same conductor (trace), you have different voltages at opposite ends.

This gives rise to reflected signals, and a host of high speed effects which you can look up and read about if you'd like. The point here is this (and yes, this is the answer). When the product in question was originally designed and developed, the specs called for a maximum transition time for all gates, digital outputs, of some maximum time period. This spec was no doubt driven by the need to accomodate certain setup and hold requirements. When the manufacturer of one of the chips "improved" their chip to transition in a fraction of the previous rating, the problem was born. It wasn't a matter of the design being borderline with the old parts. It was a perfectly good design, for the old parts. But with the faster switch times of the new chips, which still met the spec for less than the maximum allowable transition time, the traces it drove were now beyond the critical length for the new parts.

This is why faster is not necessarilly better, and in fact can be worse. And yes, in designing a circuit it would be preferable to specify not only a maximum transition time, based on setup and hold and other timing requirments, but also specify minimum transition times. My rule of thumbe is to use double the propogation time of my longest trace. And if you are ever faced with a digital circuit design that suddenly stops working, analyzing the critical trace lengths could lead you right to the problem.

Next time I want to look at splitting power planes. ADC and DAC manufacturers always tell you it's a must. But µ-controller manufacturers tell you you only need a capacitor for your reset pulse. Next time I want to look at why you probably don't need to split your power planes, and the can of worms you open when you do