| ??? 12/18/04 19:40 Read: times |
#83434 - To tell the whole truth... Responding to: ???'s previous message |
...the key difference here was not the speed of the gates, but the technology (LS->HC). There is a few pF capacitor to GND between the two gates. This, together with the internal resistor in the positive part of the LS's output stage (in parallel with the input pullup of the following gate, but that can be neglected) makes a nice and consistent delay on one of the edges, so that the speed of the gates themselves (and variation of them) can be neglected. (For Erik Malund: the C is within the specification for load capacity of LS :-). Of course there is no such R in the CMOS part's output, and the RDSon of the CMOS transistors in it is of an order of magnitude (if not two) less. As I wrote this was an "early" design of me, stupid and ignorant then (and sure today, too, but today I do not routinely design HW any more (saving my and my colleagues' sanity :-)). Today, I would rater go for a synchronous design. The digital circuits being analog, it has not only the consequence of causing problems, but can be also exploited - with care and caution, of course. The mentioned delay is an example. I also like to put an indication LED between LS output and GND - no series R. Believe me or not, this is fully within specs (but not many of them - watch the max current of VCC pin(*)) . Not that I don't have a R or want to spare $.02, just a mere provocation for those who will eventually copy them (those are hobby or experimental designs only). Jan Waclawek (*) the same applies also for "properly" connected LEDs - via R to VCC - watch the max GND pin current |
| Topic | Author | Date |
| Weekend On-Topic (WOnT) | 01/01/70 00:00 | |
| microsoft ?? | 01/01/70 00:00 | |
| Cute ;) | 01/01/70 00:00 | |
| Weekend on Topic | 01/01/70 00:00 | |
| A very reasonable hypothesis | 01/01/70 00:00 | |
| happened here | 01/01/70 00:00 | |
| The chip changed | 01/01/70 00:00 | |
| What happened? | 01/01/70 00:00 | |
| Also an excellent hypothesis | 01/01/70 00:00 | |
| too much | 01/01/70 00:00 | |
| Nah. | 01/01/70 00:00 | |
| Me too, But | 01/01/70 00:00 | |
| systematic debugging | 01/01/70 00:00 | |
| Pb-free? | 01/01/70 00:00 | |
| Did the temp characteristics change? | 01/01/70 00:00 | |
| another one from memory | 01/01/70 00:00 | |
| What it's not. | 01/01/70 00:00 | |
| Solution | 01/01/70 00:00 | |
| Speed! | 01/01/70 00:00 | |
| Speed | 01/01/70 00:00 | |
| Would get the oscope, first | 01/01/70 00:00 | |
| Try this | 01/01/70 00:00 | |
| What it is? | 01/01/70 00:00 | |
| Think volume | 01/01/70 00:00 | |
| Not a puzzle!! | 01/01/70 00:00 | |
| Apologies | 01/01/70 00:00 | |
| Re: | 01/01/70 00:00 | |
| Y2K-and-something | 01/01/70 00:00 | |
| Y2K + something | 01/01/70 00:00 | |
| Y2k05 | 01/01/70 00:00 | |
| The Unix Epoch and the Year 2038 | 01/01/70 00:00 | |
| Yet another true story... | 01/01/70 00:00 | |
| A perfect example | 01/01/70 00:00 | |
| Newer IC | 01/01/70 00:00 | |
| Answer time...? | 01/01/70 00:00 | |
| another guess | 01/01/70 00:00 | |
| language | 01/01/70 00:00 | |
| Faster does not mean better! | 01/01/70 00:00 | |
| Ok | 01/01/70 00:00 | |
| Gladly | 01/01/70 00:00 | |
| To tell the whole truth... | 01/01/70 00:00 | |
| Hidden parameters | 01/01/70 00:00 | |
| Parasitic parameters | 01/01/70 00:00 | |
| Chip manufacturer changed? | 01/01/70 00:00 | |
| Faster/slower or "controlled" rise time | 01/01/70 00:00 | |
| Answer | 01/01/70 00:00 | |
| Amazing.... | 01/01/70 00:00 | |
| Amazed | 01/01/70 00:00 | |
| Split Planes | 01/01/70 00:00 | |
| A bit disappointed... | 01/01/70 00:00 | |
| Series resistors and line matching | 01/01/70 00:00 | |
| Series termination resistors | 01/01/70 00:00 | |
| Series termination | 01/01/70 00:00 | |
| SWR | 01/01/70 00:00 | |
| simulation to the rescue | 01/01/70 00:00 | |
| Thanks! | 01/01/70 00:00 | |
| The same moment? | 01/01/70 00:00 | |
| The same moment! | 01/01/70 00:00 | |
I'm Back. | 01/01/70 00:00 |