| ??? 02/05/07 17:20 Read: times |
#132065 - answer Responding to: ???'s previous message |
I am using the SPP mode. All it is doing is providing output (code).
It acts as a rom. I intend to use highspeed CMOS devices. All my devices (except for the CPU, RAM, and EEPROM) will start with 74HC and 74HCT. The circuit is fine. It is the matter of making the connections optimal, so optimal, where I use the fewest wire jumpers. You needn't concern yourself with the address/data line arrangement on your SRAM Software wise, The address and data lines on the EEPROM/RAM can pretty much be connected to any address and data lines on the 8051. Same applies to the data lines. However, when it comes down to hardware creation, I have to connect these lines in a certain way so that I don't have to overlap wires. Also, I don't want to use excessive wires, because it looks too messy. As for speed, I'm not concerned at this point. If I have to buy a crystal with a lower speed, I will. When I write the data to the rom, I am not controlling the WR pin directly. Instead, I am constructing code on the parallel port to represent the writing (Like movx @(EEPROM address),data). I think I will need to steal a port pin for the WR pin. |
