The original NMOS 8051 was made with dynamic logic. You could actually damage the part if the clocks were stopped. As a result, Intel had to make sure that the clocks continued to run during reset. Thus, reset became more of a NMI rather than a true reset.

The original 8051 had a divide-by-two in the clock input. This in turn drove a divide by 6 state counter. The combination of these two circuits was used to generate all of the internal 8051 timing signals. Remember signals in the original data sheet called S5P2 (State 5, Phase 2)? This timing logic was not reset by the reset signal.

Lack of a reset meant that is was hard to sync up to a running 8051, since it could randomly be in any of 12 different states. This makes the part hard to test, and so Intel added a true reset to the part. Since the part is already in reset when you activate the true reset, all that the true reset does is reset the divide-by-two and the state counter.

I have found this to work on every 6X and 12X NXP and Intel part I have looked at:

Stop the clock, wait 100 ns, bring PSEN and ALE low for 100 ns, wait another 100ns, and resume the clock.

Side effects can include smoke, fire, and cancer.