and even the "Rolls-Royce":

http://www.cygnal.org/ubb/Forum...6.html

I reread the whole link and

1)
Brent W (a SILabs person) writes
Leo,
We take FLASH corruption very seriously and would like to work with you to identify and solve the problems you are seeing. In extensive testing, we have not seen any instances of FLASH corruption during power-cycling tests on the 'F124 when the VDD monitor has been properly enabled.

2) there is no one that have reported memory loss problems with this chip that do not either have brownout detection (MONEN) disabled or have flash write routines in their code.

so 1) refutes Richards "the manufacturers do not care" and 2) show that my "gut feeling" that chips with plenty analog tend to have better reset circuitry. This stem from a statement from a manufacturers rep "it is difficult to integrate analog circuitry on a digital chip". So when the hurdle of including analog circuitry has been overcome, it is possible to make a decent reset on-chip. Now this made me curious and I asked myself "did you?" and yes, I did. I must retract my statement "I always include a supervisor" On a one uC board (I would not do it on a multiprocessor board) of mine with a f124 there is no supervisor. This design is about 3 years old and 1000+ boards (CHROMA version 2) are running in a harsh environment without any memory loss. I must add that I added a 4k7 resistor from reset to Vdd since the pullup internal to the chip is rather high ohmed.

Erik