What I see myself doing here is combining six MCU's, half of which have reset IC's and half of which do not. Each MCU should contain precisely the same code, and all unused locations should be readily verifiable with some superficial method, e.g, data = !address, in both ROM and RAM, the RAM being ordered by the MCU. The MCU's then are run up to normal operating voltage, which is allowed to settle, all the while held in RESET, with the oscillator running and counted for some number, perhaps 2K or 4K cycles, and then reset is negated. Now, with external logic, the outputs of each set of three are compared, among one another, using majority logic to point out discrepancies, which are recorded, though only by cycle number and location of the anomaly, and also compared with the other set. This provides an opportunity to record the number of failures within a large number of cycles, which could be varied in operating voltage, noise amplitude and character, etc, with a minimum of effort and using only a minimum of data. The result will be a record of how many times, under what sort of stress, an error occurred, and in which set they occurred under which circumstances. It's not yet clear to me which parameters should be varied and in what combinations they should be varied.

I imagine that on-board capacitors should be very nearly discharged, probably by means of semiconductors that can handle a substantial amount of current, and the supply rise and fall times can be controlled externally.

A large number of iterations can be processed this way, and recorded, without the task becoming burdensome during its progress. The MCU circuits should be on the same PCB with the same ground and power plane. So long as conditions are reasonable, they do not have to be perfect, i.e. Vcc<=>GND noise doesn't have to be held down under 5 mv, temperature variations of a few degrees C shouldn't be a problem so long as the ambient temperature is consistent for all the MCU's.

I'd be interested in what stresses you'd find useful, and what sorts of operations you think would be warranted within the MCU's. Some other controller will have to govern when the code has to be refreshed in all the MCU's, so I imagine this is one case where a CRC might be of use. That way, rather tha dumping the entire memory for comparison, which might take a relatively long time, it could simply dump the CRC, which would indicate its code is still valid.

RE