??? 03/02/07 15:04 Read: times |
#134099 - Good chips and state machine failures Responding to: ???'s previous message |
Erik asked: with a 99.995% requirement and a supervisor with a proper treshold what is the chance that "state machine failure" would be a problem with a chip that has passed initial tests and otherwise works. This is not a case of a defective chip. When powering down, you are operating the chip outside of the data sheet specification. Eventually, every component of the uC will stop working as Vdd goes to zero. Unfortunately, they all don't stop working at the same time. And to complicate matters, the relative timing between logical paths will change depending on the types of logic used in each path. And so a state machine can change states on power down. Probability that it can: 100%. Probability that it will: who knows. Probability that it will cause a problem: overall - small. We are getting rather theoretical here. Chips can glitch internally and externally during power down unless steps are takes to insure that the glitches don't matter. I once worked on a bomb fuse that had a glitch on the FIRE output pin whenever it was reset. |