Yes, but this to occur, you need the clock keep running at least for the state machine reaches the point where it updates the ports, isn't it. So you can't simply stop the clock when the reset occurs. This contradicts (slightly) the following part (OK I see the "and then stop the clock" but it should be more specific perhaps):



Moreover; my understanding of things is, that the sate machine produces a sort of the clock which once in an instruction cycle (or two) clocks the reset into the output pin latch. Now isn't it the very same state machine - or even the same clock/latch signal - which enables any change to the output pin latch? If so, failure to produce a valid clock which would reset the pin means also the failure of any mechanism which would change the state of the pin otherwise! In other words, the reset should be enough to keep the pins high, no matter if clock present or not. (I know we are talking grey area where anything may happen, but assuming - I believe correctly - that CMOS works correctly in a limited way (slower) to much lower than the specified VCC). And the CMOS latch on the output should hold its value quite well until the complete death of VCC - note how well CMOS SRAM memories hold their value even with almost completely zero VCC...

I am not talking about FLASH corruption here yet, only "agonical wiggling of pins".

Btw., I cannot stress it enough - and Erik already mentioned it in this thread, too - the reset signal MUST be distributed across the whole system.

Jan Waclawek