Judging from the timing, I have to assume the circuitry, the function of which they've integrated into the DS89C4x0 series, is that of their DS1232. You're right, of course, in that the die is very much noisier than the PCB. What goes wrong, however, happens on the die, and not necessarily on the PCB.

What's interesting about the Maxim/Dallas chips, however, is that they revised their silicon to address the flash-corruption issue. Did anyone else do that? It called attention to their series when they published their flash-corruption errata, in that they had brownout-control, reset circuitry, and a watchdog, all integrated into their chip, yet it did not mitigate the flash corruption issue. This is what piqued my interest in the nature of this and other reset/brownout related problems.

What I've found so far is lots of discussion and conjecture, but not very much rigorous testing.

I don't deny any of the comments you, Kai, and others have made. It's a difficult issue to approach with rigor, which explains why manufacturers have avoided it. Needless to say, I won't be able to test hundreds of units (a) becuase there's not enough time, and (b) because I'm not willing to buy hundreds of units of any MCU with a history of this problem, particularly just to test them, which will benefit me not at all.

However, I find that it won't be hard to produce a test fixture that accomodates two sets of three MCU's. If this houses six identical MCU's, the outputs from which are all compared, any anomalous output would be detectable. If their clocks and reset are precisely synchronized, it should be easy to cycle them equally by altering their power and reset signals, and monitoring their respective outputs. With a proper low-impedance ground and power distribution plane, controlling both high and low-frequency noise is less complex, and control of rise and fall times of Vcc is straightforward.

I don't anticipate that any one will change their practices, as most will not even read the statistical report that's generated. It should, however get the attention of thoughtful designers, that manufacturers were, and stil are, unwilling to invest the very few hours of effort and a few weeks of automated recording time, in order to shed light on this annoying problem in a statistical and quantifiable way. The benefit would be that designers can examine the result and interpret them based on any statistically significant deviations from established "normal" or "nominal" behaviors. Of course, the "nominal" conditions must first be established, as the "recommended" operating conditions are clearly too broad.

I don't anticipate that anyone will "fix what's not broken." If, like Erik, you find that all your circuits always function perfectly, you'll never have to consider any changes. I'm not convinced that the majority of readers of this forum are even remotely concerned with reliability. Most, I think, simply want their ONE 805x project to function adequately, on occasion, with a very forgiving definition of "adequately."

As for me, I want a simple way to reset the 805x such that it doesn't damage its own program store, and so that it genuinely resets itself when told to do so.

I've asked about this in a number of different ways, but always get the stock response, "Why would you want to do that?" which, of course, is what the chip makers have been tossing at us for over a decade. What i want to do is to quantify how much better an 805x behaves with a commercial RESET/supervisor IC than without one. This has to be tested under both "friendly" and "unfriendly" circumstances, namely rapidly as well as slowly varying supply voltage, both high-frequecy and low-frequency noise on the supply, rapid and slow rise and fall times at power-up and power-down, free-running vs. gated oscillator to the MCU's, and probably a lot of conditions that I haven't yet considered.

All I've done here is to offer to do something that the chip-makers should have done a decade ago, and perhaps did, but didn't publish, so that interested parties can be made aware of the benefits, costs, limitations, tradeoffs, etc, involved in designing with these parts.

I'm not in a hurry to go forward. It's not a terribly difficult thing to do. The time involved consists mainly of waiting for the process to end. That's why it puzzles me that chip makers haven't published any results. If nobody's concerned about this I won't bother you guys with it henceforth.

RE