??? 03/02/07 14:21 Read: times |
#134092 - Flogging a dead (reset?) horse Responding to: ???'s previous message |
Erik said: NOTHING IS GING ON when the chip is in reset.
When Vdd is within spec, I agree. But consider the power down case. Different logic blocks have different minimum operating voltages. As the chip powers down, some sections will stop working before others. And so the external pin can be held at reset, but the internal processor could start running away if the reset logic is the first to fail. I can't speak for all derivatives of the 8051, but for the Intel and NXP, 5 volt, 6 and 12 clockers: The reset pin is sampled by a small state machine which in turn controls the internal reset signal. And if state machines didn't fail, then we wouldn't be having this thread. |