??? 03/02/07 14:33 Read: times |
#134094 - Stopped clocks and reset Responding to: ???'s previous message |
Erik said: Lynn, pray explain what is the difference between a uC with the clock stopped and a uC held in reset. This is not an either-or case. When reset occurs, the flops in the port are set. Since they are now "one", the outputs are high impedance. They will remain that way when reset is removed until someone writes a zero to them. A better solution is to let the brownout case reset the part, and then stop the clock. If it is a true brownout, then it is a simple matter to start the clock again without having to wait for the oscillator to start back up. And if it is a true power down, a stopped clock minimizes the chances that something else will go wrong (like jumping to an IAP routine) before the power reaches 0 volts. It is an engineering equivalent of how do you keep cool when everyone else is panicking. |