??? 03/02/07 17:51 Read: times |
#134118 - Let's be general Responding to: ???'s previous message |
Erik Malund said:
block the oscillator when the power is below 90% might be the answer to the power-down transient case.
I think that is a very good idea. ... This sure solves the problem of a runaway processor. Lynn, pray explain what is the difference between a uC with the clock stopped and a uC held in reset. I know of two: in reset the port pins will be high, just stopping the clock will leave them where they were. Another issue: during a slow power down (draining the storage caps) how will the port pins behave if no reset but oscillator stopped. Erik PS: as opposed to Richard, I am discussing these new-fangled derivatives that are static CMOS, not the dynamic devices of yesteryear. I'm not focused entirely on the old NMOS parts, Lynn. I'm looking for something that covers the general case. However, for now, I'm trying to define the problem(s). I've seen a case where the Philips 80C32, which clearly has no FLASH involved, runs away during/after reset. Because I do quite frequently, as a proportion of what I do with 805x's, have to deal with old-style circuits into which I want to drop new MCU's, I'm concerned with flash corruption, at least sometimes, and therefore need to know what the root of the runaway problem, as well as the flash corruption problem, is. The reason I have this "bee under my bonnet" is that I've never seen a white-paper or other serious technical document dealing specifically with the problems associated with power transients and reset. The fact that I've been able to observe peculiar behavior such as the differences between power supply types, has piqued my interest. Now I'm considering building and running a test. Whether I actually do it is TBD. RE |