FPGA's are essentially RAMs with feedback. On powerup they have to be programmed, which is generally accomplished with a dedicated prom that "talks" a specific protocol the mating hardware to which is built into the FPGA in order to effect boot-up. FPGA's are typically built around logic cells based on RAM lookup tables that are used to generate logic functions. Other RAM elements are used to control routing, and the remaining RAM resources can actually be used as distributed RAM. There are often also RAM blocks for use as, ...well... RAM. FPGA's have LOTS of logic cells, hence, LOTS of registers, which facilitates synchronous design. They can be said to be register-rich, and logic-poor, though that's quite relative. Timing can be quite variable due to routing and resource concatenation delays. This can impact pinout, or, pinout can effect final timing results, which can be annoying. FPGA's have, generally, MUCH more logic than CPLD's, and therefore require much closer and more careful planning than CPLD's. Cost per "gate" (a much debated metric) is generally very low, but minimal gate counts are generally quite high, in some cases approaching 10 million gates. Unfortunately, the marketing department determines the relative gate-count.

CPLD's have electrically programmable nonvolatile memory to control their configuration and hard logic, typically configured as arrays of what amounts to a quite-large (often 16-18-inputs) AND array feeding an OR array of as many as 18 inputs, which in some cases is also programmable, and that feeding a macrocell consisting of multiplexers and buffers with a flipflop at its core. That flipflop can be configured to be used or not in the macrocell, thereby producing a combinatorial or a registered output. Macrocells can be direct outputs, or buried. They can drive pins or the input logic array, via feedback. CPLD's can be said to be logic-rich and register poor, as their register count seldom exceed their I/O pin count by much more than two. One of their strengths is that their timing is entirely deterministic and therefore, generall, though there are exceptions, their pinout is entirely deterministic as well. CPLD's allow the board design to proceed when the pinout is assigned, and, unlike FPGA's, changes in the internal logic seldom affect pinout or timing. Cost per gate is high relative to FPGA's, but the device size in gates is quite a bit smaller than even the smallest commercially interesting FPGA's.

Designing a small CPLD, e.g. 64 Macrocells, typically takes about two hours from inception to programming once requirements analysis is complete. It can take quite a bit longer, though. A very small FPGA, of 100K-gates can take a whole day, and often takes a week, depending on lots of variables.

FPGA's, being RAM-based have the advantage of faster technology than CPLD's, as integrating nonvolatile memory to hold configuration abetween power cycles makes them slower.

There is lots of IP available for incorporation in FPGA, which costs money but saves lots of time. These IP products are generally quite straightforward to implement, though there's "many a slip 'twixt cup and lip." YMMV!

RE