| ??? 03/27/07 06:03 Read: times |
#135950 - ba humbug!! Responding to: ???'s previous message |
Richard Erlacher said:
A good, fast PLL will acquire within 20-40 reference clock cycles and track over twice its capture range. These DLL's take millions of cycles to settle and, essentially, are essentially useless for purposes aside from clock distribution within the FPGA. Youve really got to stop making such wild claims.I have used the DLLs and they exactly what they say on the tin,they capture within 16 cycles and using the unisim library for xilinx in modelsim you can see they behave exactly as you would expect. You have to remember that sales people for companies like xilinx know nothing and if you ask them about DLL capture range their little heads spin round. You say stuff such as 'These DLL's take millions of cycles to settle' and yet they simply don't. |
