A good, fast PLL will acquire within 20-40 reference clock cycles and track over twice its capture range. These DLL's take millions of cycles to settle and, essentially, are essentially useless for purposes aside from clock distribution within the FPGA.

I frequently run into situation where I have a single data source, at very nearly (within 100 ppm) the same rate, but, not exactly the same rate. A single bit-frame-slip, however, will screw up an entire message acquisition. Therefore, I need a PLL that acquires within a very short time, tracks over the entire +/- 100 ppm range, and allows me to switch from one input to another pretty much seamlessly, based on the PLL's "locked" output.

The XILINX writeup on their SPARTAN DLL suggests that it will acquire lock within 16 cycles or so, yet when I've inqured with them aobut it, they behave as though they'd never heard of things like acquisition time, lock range, tracking range, etc. Some of their spec's suggest that it takes millions, or even billions of cycles (seconds rather than microseconds) to acquire lock. It would seem that one could reset the DLL and switch the external input to the DLL during the RESET, but the extremely ambiguous spec's seem to contraindicate that.

Unfortunately, companies such as Philips, which acquired Signetics back in the late '80's, no longer makes PLL's such as the NE564, which were capable of oscillating and operating at 50 MHz or so. Their HCMOS parts aren't common either, and they don't operate above 17 MHz. If I have a number of synchronous data sources and need to acquire lock inside 5-8 microseconds, I'm screwed. I have to build an analog PLL from the ground up, since there are no longer any VCO's that operate in the right range.

RE