| ??? 03/26/07 21:52 Modified: 03/31/07 06:11 Read: times |
#135941 - Maybe it\\\'s not so odd ... Responding to: ???'s previous message |
Andy Peters said:
Richard Erlacher said:
That flash-FPGA is their MAX-II isn't it?
Sadly, they're RAMless. MAX-II sounds like an Altera CPLD. I must have gone to sleep. They are ALTERA CPLD's but have architectural features similar to FPGA's. I read Lattice, but thought ALTERA. I was simply responding to my disappointment with ALTERA's failure to work out a useable flash-based FPGA. They've tried it before, doncha know ... The Lattice flash-based FPGAs do have both block and LUT RAM. Quite so ... though I haven't gotten up-to-speed on them yet. I occasionally need an odd configuration, e.g, 300 k-gates in a 16-pin package, (4 4/O's) That's quite odd. Well, maybe, but only because the die wouldn't fit. If I need 2-dimensional FFT's on a video bitstream for scan-rate conversoin, and need only Ri, Gi, Bi, and CLOCKi in, and Ro, Go, Bo, and CLOCKo as outputs, who needs the other 240 pins? or 50 k_gates with 500Mbytes of block ram.
MEGA bytes? Extreme case, mayabe, but suppose you want to store an entire frame of high-definition TV so that you can process it into a format compatible with a 4096x2560 monitor in real time? All that while runing LINUX on the coresident CPU with 4 DSP's and associated hardware. No external SDRAM can be kept up. Real PLL's, too, not those ultra-slow, Tacq=two-liftimes things they use for clock distribution. Too bad nobody cares what I want ... ... Oh, you should read how Xilinx can't make up their minds whether the DLL or the PLL is superior. -a My first question would be, "better for what?" Have you got a pointer to that debate? RE |
