There are Costas Loop IP's for the XILINX series FPGA's, but they're several (~5) orders of magnitude too slow. I need something that acquires syncrhonization with a 20 MHz modulated (e.g, Manchester-encoded), data stream in about 4-5 microseconds. Most of these IP's operate in the 8-15 kHz range and acquire lock in 40-50 ms.

Also, isn't the Costas Loop for use with suppressed-carrier phase-modulation? It produces, among other methods, a phase ambiguity that has to be resolved, too. That's not a handy thing to have when you're using Manchester == BPSK.

I've seen discrete implementation examples, but have never successfully implemented one of them. See

http://www.lll.lu/~edward/e.../proj1.htm

for one example.

RE