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???
03/28/07 00:08
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#135989 - I considered that ...
Responding to: ???'s previous message
While I've run many simulations, I've not yet attempted to use the things. The Spartan-II DLL also requires a reset prior to lock, but since I'd be switching inputs, albeit inputs all within a very close tolerance (100 ppm, I'd guess) I'd know to reset the DLL and when to do it. There's a fair amount of literature that seems to muddy the waters as to what the acquisition time, tracking range, and capture range would be. Needless to say, they (XILINX) don't want to attempt to characterize their DLL in such PLL terms.

One issue I've been trying, occasionally, to resolve, is whether the DLL can be used to acquire lock to a modulated data stream, in which there are frequent "missing pulses". Consider a manchester-encoded data stream, or, somewhat worse, an MFM- or GCR- encoded data stream. I've been totally unable to get any data on how missing pulses affect the behavior of the DLL.

I appreciate the ready availability of 4 phases of the input clock, and of the ability do double, or even quadruple the input clock. Until I get details, however, it's a test project, and I will probably never have the means to establish an adequately broad sample base.

Andy, is that the Spartan 3E "starter kit" that you're using? I've got one, but, due to the rather odd and rather flimsy connector I've not wandered into experimenting with it. What have you observed with that board, so far?

RE



List of 61 messages in thread
TopicAuthorDate
FPGA            01/01/70 00:00      
   Why on EARTH would you ask that stuff here?            01/01/70 00:00      
   Triscend, Zylogic, Actel            01/01/70 00:00      
      Triscend\'s gone quiet ... is that permanent?            01/01/70 00:00      
         Triscend is dead - now it's Zylogic            01/01/70 00:00      
            re soft-cores            01/01/70 00:00      
               So far, I've not encountered one that works at all            01/01/70 00:00      
         Published ?            01/01/70 00:00      
            Published => open source=> free, as in free beer            01/01/70 00:00      
      Actel Core8051 and Core8051s - "free"            01/01/70 00:00      
         Everyone I know refuses to use actel FPGAs            01/01/70 00:00      
            A good word for Actels            01/01/70 00:00      
            Good question            01/01/70 00:00      
               what we used to do when we gave out evaluation            01/01/70 00:00      
   VHDL Tutorial            01/01/70 00:00      
      Thanks,            01/01/70 00:00      
   Don't forget to read my extremely wonderous            01/01/70 00:00      
      ... and this thread, from a few months ago ...            01/01/70 00:00      
         so ... what did you ever do?            01/01/70 00:00      
            Not really, things change            01/01/70 00:00      
               sounds like '1553            01/01/70 00:00      
                  Yep and the optical version            01/01/70 00:00      
            I got a job!            01/01/70 00:00      
               Good for You!            01/01/70 00:00      
   related question            01/01/70 00:00      
      CPLD and FPGA            01/01/70 00:00      
         I'm not so sure ...            01/01/70 00:00      
      different feature sets, among other differences            01/01/70 00:00      
         I know the differences, thus my question            01/01/70 00:00      
      what happened?            01/01/70 00:00      
         Numbers ... what are the numbers?            01/01/70 00:00      
            Think of a number            01/01/70 00:00      
               FPGA with built-in config flash?            01/01/70 00:00      
                  RAM and Chips            01/01/70 00:00      
                     Maybe, but my needs are "different"            01/01/70 00:00      
                        you need to rethink your bga figures            01/01/70 00:00      
                           It\'s a culture thing ...            01/01/70 00:00      
                              Ive had a design reverse engineered            01/01/70 00:00      
                                 Comments and FPGAs            01/01/70 00:00      
                                 I've had one outright stolen ...            01/01/70 00:00      
                                    Design Security            01/01/70 00:00      
                                       do you report them            01/01/70 00:00      
                                          Reporting Crooks            01/01/70 00:00      
                  huh?            01/01/70 00:00      
                     last I heard xilinx still liked DLLs            01/01/70 00:00      
                        Unfortunately, they're useless as PLL's            01/01/70 00:00      
                           ba humbug!!            01/01/70 00:00      
                              not quite sure what happend there            01/01/70 00:00      
                              not so fast, Jez            01/01/70 00:00      
                     Maybe it\\\'s not so odd ...            01/01/70 00:00      
                        your application requirements are odd!            01/01/70 00:00      
                           I don't recommend against 'em            01/01/70 00:00      
                              evidently "my world' is unreal            01/01/70 00:00      
                                 Perhaps it is            01/01/70 00:00      
                              DLLs and locking            01/01/70 00:00      
                                 I considered that ...            01/01/70 00:00      
                                    re: I considered that ...            01/01/70 00:00      
                                       Consistent with my prior statement            01/01/70 00:00      
                                          you should try using a costas loop            01/01/70 00:00      
                                             That\\\'s for suppressed carrier, isn\\\'t it?            01/01/70 00:00      
   did u refered altera            01/01/70 00:00      

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