| ??? 03/27/07 15:52 Read: times |
#135964 - not so fast, Jez Responding to: ???'s previous message |
Jez Smith said:
Richard Erlacher said:
A good, fast PLL will acquire within 20-40 reference clock cycles and track over twice its capture range. These DLL's take millions of cycles to settle and, essentially, are essentially useless for purposes aside from clock distribution within the FPGA. Youve really got to stop making such wild claims.I have used the DLLs and they exactly what they say on the tin,they capture within 16 cycles and using the unisim library for xilinx in modelsim you can see they behave exactly as you would expect. You have to remember that sales people for companies like xilinx know nothing and if you ask them about DLL capture range their little heads spin round. You say stuff such as 'These DLL's take millions of cycles to settle' and yet they simply don't. It's too bad the documentation for these features is so muddled. When I've specifically inquired about using DLL's in the way I suggested, I've been given a list of somewhat ambiguous and certainly inconsistent writeups, some specific to Spartan-II DLL's and some referring to Virtex DLL's and Spartan-II DLL's in the same context, though elsewhere they say the two are different. I've been referred to writeups that state precisely what I said, that it takes a very long time for a DLL to reestablish lock once the source signal has been lost, gated off, etc, then resestablished. The library description is in conflict with some of the writeups to which I've been referred, though, they're almost universally targeted at the Virtex DLL, which they say differs from the Spartan DLL, but never get around to saying in what way. The result has, so far, been that I've never bothered with 'em, choosing instead to use external PLL's, which is a pain in the gluteus, but gets the job done. Perhaps you can shed some light. I'm certainly interested. RE |
