Please believe me, when I say that I had no intention of insulting anyone. However, your second example DOES, indeed, point to what I've considered to be the REAL problem all along.


It's not "proof" that I seek, but, rather, a different approach to the analytical logic. Peripherals, including memories, as you point out, need to be protected, but I don't think they need to be protected from the change in Vcc. I have become persuaded that they need to be protected from the MCU. The RESET circuitry doesn't do that if the voltage is fluctuating slowly.

I believe, and perhaps you'll agree, that the "reset-related" difficulties that people describe, can also be attributed to power-down-related misbehavior of the MCU, at a time when the effect of RESET is undefined, namely, when Vcc is falling and outside the range within which the MCU's behavior is characterized.



in the cited example

Jan,

I believe the problem to which everyone likes to refer as the RESET problem, the REAL issue is Vcc rise and fall time, not to the logic or the external peripherals, but to the MCU, because that's the engine that can run away and do things while power is fluctuating. I believe that these problems will "go away" if a RESET/Supervisor IC is used not just to assert RESET, the consequence of which is not so well defined, but to stop the oscillator and/or lower Vcc to within a silicon junction of GND.

It's easier to use the negative-RESET from, say, a MAX1232 to stop the oscillator than it is to drive a transistor with the positive reset, processed in some as yet undefined way to delay it so it really can generate a RESET pulse to the MCU when appropriate, but dropping Vcc nearly to GND each time the RESET signal is asserted might provide a clue. I do believe these problems are infrequent enough that truly testing and monitoring a circuit, in a way that would make the result applicable to a large majority of other circuits, might be quite a challenge.

I've never doubted that there's an inherent weakness in Intel's approach of using positive-going reset and interrupt signals to its processors, but I also believe that the problems often attributed to RESET in this forum are probably less RESET-related and more Vcc-rise/fall-time related.

I'd like to shift the focus of this particular thread, which is very relevant to this set of problems, from a virtual argument over whether use of a RESET/Supervisor IC is warranted, to a more precise discussion of how the problems associated with RESET are observed and how their "solutions" are verified.

I'm presently persuaded that the problems are cursorily observed, in most cases, without any thorough study, and the "fix" of introducing a RESET/Supervisor IC produces a significant change in circuit behavior that the technician/engineer implementing it finds to be a relief, and, therefore, gives it his blessing, despite the fact he's actually done no thorough, rigoroous testing to verify that the "problem" itself has been alleviated. He's simply happy that the obvious observability of the perceived problem has been shifted in some way.

RE