| ??? 10/05/07 05:54 Read: times |
#145443 - more questions... Responding to: ???'s previous message |
Richard,
thanks for the explanation - though, it gave rise to MORE questions... Richard Erlacher said:
Well, YES, though, at first, those signals were observed indirectly via the four gates of external logic that I used to generate the select and enable strobes to the BBRAMs. There is nothing wrong with that, provided that 1. they had enough VCC all the time, 2. all the inputs came from the '51. The '51 is supposed to be "quiet" on ALL of its pins while RESET is asserted. Richard Erlacher said:
As I mentioned yesterday, however, I didn't get any pictures because it was not a rigorous study. I used two oscilloscopes, one, a 4-channel TEK 2467B and the other, a 2-channel TEK 475A where I was using the single-sweep mode just to detect activity on nWE with the threshold set far enough from where I "thought" it should be set to avoid being influenced by random noise, of which there was, in fact, very little. Do I understand it right - does this mean that the trigger was connected to VCC and set to say 4.5 V trailing? Was it connected directly to the VCC pin of '1232? Are the VCC pins of all involved chips ('1232, '51, RAM, '00) conductively connected all together (I mean: aren't they supplied from a different supply chain)? Isn't GND of some of these chips disconnected by chance? Also, did you actually SEE the RESET (as measured directly on the RESET pin of the '51-s) going ACTIVE when VCC has fallen below the threshold? I am asking this, because you mentioned the '1232 was an afterthought - couldn't there be something possibly rendering RESET invalid - for example haven't you left the RC in place, together with the '1232? What happens if you press the reset pushbutton (or ground the respective '1232 input in any other means)? Are the memory selection signals still active? Jan |
