| ??? 10/02/07 22:13 Read: times |
#145270 - just how would YOU predict the behavior, Jan? Responding to: ???'s previous message |
Jan Waclawek said:
Richard Erlacher said:
If Vcc isn't at a legal level, it's unlikely that RESET is, either. By that time, the MCU is operating in that region wherein its behavior is entirely unpredictable, and the so is the supervisor. First, it's a common misconception, that the behaviour of an mcu, or supervisor for that matter, at low power level is UNPREDICTIBLE. It IS predictible to a great extent, although often not stated so by the manufacturer explicitly. We can derive much from first principles, though. If you have no guidance from the manufacturer, and no statistical evidence, how can you presume to predict what a component will do as its supply voltage falls out of specified limits? What are the underlying assumptions, and what is their source? As the vast majority of IC of today are CMOS, there is no reason to deal with anything else, but similar reasoning can be derived for any technology.
A CMOS structure works statically down to the biggest of the two threshold voltages (of the PMOS and NMOS transistor), below it one or both remain closed permanently. The particular voltage where this happens is process dependent and variable, but that's not the point here - for most 5V processes used in '51 compatible MCUs it is certainly below 2V which is the retention voltage of the internal SRAM. The trip voltage for the nWE lockout of the BBRAMs I used is considerably higher than 2V. Nevertheless, I observed MCU activity during RESET asserted by a MAX1232 during a very long (not measured) decay of Vcc that selects and, it would seem, ultimately corrupts the BBRAM. That suggests that the problems occur during that part of the decay after RESET but before the BBRAM disallows writes. Boththe BBRAM and the MCU in question were Vcc = 5.5 .. 4.5 parts. One of the thing I'm considering is powering the BBRAM through a diode, thereby reducing its Vcc a bit to get the trip voltage to be reached sooner. There's probably a point between Vcc and Vcc-0.7 or so, that will have some effect. Perhaps that's where the corruption issue will be forced to the surface. But why is then the minimum VCC specified at, say, 4.5V? This is because the CMOS structure becomes slow at low voltages, maybe too slow to follow the crystal imposed clock properly. Above the threshold voltage, a sequential circuit (flipflop, latch) may or may not react on a fast clock; but either it will do what it is supposed to do, or it will remain in its last state. CMOS is slow, but even the old 1970's 4000-series CMOS would support a 12 MHz crystal oscillator. If the oscillator were at, say, 50 MHz, I'd worry about CMOS at lower voltages, but current technology is much faster. Now, if you do have a mechanism which forces the critical flipflops (output latch and FLASH charge pump interlock) into a "known good" state when the VCC starts to fall but is still within full speed operational limits - and this mechanism is known as reset, which a prudent engineer sets some 0.15V above VCCmin, and which effects within 2 machine cycles after assertion, so the prudent engineer should perhaps check there is enough charge in the decoupling caps to keep VCC above VCCmin for that microsecond or so - and if the reset continues to be active down to the threshold, for the case the flipflop would "react" somehow to the clock at lowered voltage - these flipflops will remain in the "safe" position all the way down to the threshold.
Around and below the threshold, the FLASH pump won't work either, so we are safe. Also, chances are, that most of the external circuits won't work by that time (e.g. motors which could cut your hand or so), so we are safe there, too; unless some separately powered (e.g. battery backuped) circuit is still "alive" and unaware of the powerdown state of the mcu. Of course, the prudent engineer makes an analysis in this regard. Well, unfortunately, during Vcc decay, those pump cap's are already fully charged and ready to go. As I've often pointed out, a big part of the RESET weakness is that Vcc decays too slowly. Draw your own conclusions.
JW RE |
