| ??? 10/03/07 20:50 Read: times |
#145331 - IF you're using too weak a PSU Responding to: ???'s previous message |
Erik Malund said:
Richard Erlacher said: correct if you are NOT using a supervisor, so you just posted an argument for using one Too slow a rise time can lead to a dodgy RESET Not exactly. I did indicate that if the rise time of Vcc was slow, the PSU was inadequate. I found that positive-going reset, interrupts, and the like were silly, since they couldn't be wired-ANDed and since TTL really couldn't drive an active low to a high.
1) I find the ability to wire OR much more advantageous I'd be interested in how you do that with a signal that's active-high and pulled down, yet driven with a totem pole. 2) who on eatrh would, these days. use a TTL supervisor? Who knows? I doubt there were such things when TTL was the prevailing technology. I decided not to use products with a positive reset or interrupt back then, because there were no appropriate open-emitter drivers available at the time. That's what you'd need to wire-or a positive-going signal driven by multiple sources. BTW, the RC-reset does work OK with bidirectional resets, as some 805x products have.
never heard of a "bidirectional reset" give a link, please http://datasheets.maxim-ic.com/en/ds/DS8...89C450.pdf There are others, IIRC, whose low-voltage detection and/or watchdog timers drive RESET. I think they're ATMEL parts, so I don't know for sure. Maybe Jan knows. If Vcc is out of spec, what is the MCU going to do with a RESET that's not at a valid Vcc level? How will it interpret the signals from other internal resources, flash, etc? a "valid signal level" for CMOS is Vcc-x or Gnd+y from the DS89C430..450 datasheet, http://datasheets.maxim-ic.com/en/ds/DS8...89C450.pdf page 2:
Reset Trip Point (Min Operating Voltage) (Notes 2, 3, 4)
min typ max
VRST 3.95 4.125 4.35 V
Since the RESET level is dependent on Vcc, I suspect you can't get a valid RESET when you don't have a valid Vcc. see above Well, there's at least one case (see above) where that doesn't hold. I'm of the opinion that RC is an adequate power-on reset.
I agree buyt also state it is a totally inadequate power off reset. Erik PS now that you are 'investigating' why not just try a very slow clock and see how low the uC actually works. I am conviced that all DC paths in a uC stay valid to a very low Vcc. Just think of the NXP LPC 'glitch' that for the internal reset to go away Vcc must go lower than 0.4V before it rises. Why would I do that? I've already observed that a Philips MCU clobbers BBRAM with RESET held high by a supervisor while Vcc is decaying, but before the trip point for the nWE lockout occurs. Similar things have happened on DS89C420. I'll be revisiting that for a more detailed observation. RE |
