Jaykrushna, only because you hadn't problems with RC reset so far does not mean, that RC reset is a suited methode!

Be warned, Flash micros which can change the code space memory content by themselves, for instance the ones that show ISP (In System Programming) facility, can be rendered entirly useless by even only one improper reset event!!!!

If due to an undervoltage situation the internal ISP routines are erroneously invoked, the micro's code memory content can be eroded. This was and is reported by all manufacturers of flash micros. There are tons of errata, application notes and papers which all conclude, that an ISP capable flash micro MUST have a reliable reset under all undervoltage situations.


The only secure way to prevent such a code memory corruption is the use of a good reset controller, which delivers an absolutely reliable reset signal under ALL undervoltage conditions.


Theoretically, the same can be realized with a supply voltage that is switched-on an -off instantaneously. But this is only a theroetically practicable way, because instantaneous voltage changes mean infintely high current spikes (due to I = C x dU/dt), which cannot at all be recommended as a standard design practice. Also, there must be a sophisticated turn-on- and turn-off-control of supply voltage, which always provides sharp ons and offs, even during mains voltage dips and other brown-out conditions.
Practically feasible turn-ons and -offs will always last long enough that a code memory corruption can still occur. So, you will always have to provide a proper reset.


Besides, it's very simple to provide such a reliable reset. Look at the follwing example circuit containing a MAX1232 and the AT89S52:



Different flash micros might need different reset solutions. Some might even contain such a reset funtionality internally already. But all are same in that they don't rely on a simple RC reset!

A last hint: Above scheme shows a pull-up resistance at RESET input. This guarantees a proper reset signal even when the supply voltage falls down to 0V: The external pull-up and the internal pull-down resistances form a voltage divider, that forces the RESET input high when the NMOS- and PMOS-FETs at output of MAX1232 are becoming high ohmic at very low supply voltages.

Kai