| ??? 10/03/07 05:26 Read: times |
#145280 - Clearly, we see things differently Responding to: ???'s previous message |
Kai Klaas said:
Richard said:
As Lynn Reed once pointed out, the 805x has no RESET, but, rather, has an NMI that's labeled RESET. What guarantees that it executes that NMI correctly once the voltage has fallen out of specifications? That's only half the story. The original '51 was a dynamically working micro, the clock frequency must not go under a certain limit. The reset also was dynamically working, means worked like a NMI. But today's CMOS clones show a fully static operation. Well, Lynn Reed wasn't describing the the "original" NMOS parts when he said that, was he? His company, TEKMOS, builds CMOS. Many even have an asynchronous reset, which immediately resets the port outputs when bringing the RESET pin high, independently of the oscillator and all this dynamically working stuff. Yes, there are even some with negative reset, which I like a lot better. I've not encountered a datasheet that clearly states that the reset is asynchronous and what it does, though. Where did you encounter that? So, why shouldn't be there an internal section, which is statically working and which stops all the internal flash code memory changing micro routines, whenever the RESET pin is brought high? A section which later was added, when the micro learned to write to its own flash code memory?? I'd be the last one to say there shouldn't be such a thing. I've seen no indication anywhere, yet, that suggests that there is, however. Logical as it may seem, I have to wonder, "Why do you believe that?" For me the situation is entirely simple: There's an internal section, which disables all the ISP micro routines, whenever the RESET pin is brought high. This section works statically and behaves as intended up to a certain minimum supply voltage, let's say 2...3V. Down to this level the reset controller must guarantee a stable high at RESET pin, Yes, if it were so, but then, what is a stabile "high" when Vcc is changing, and where is it generated? but which is no problem at all. When then the supply voltage further goes down, and this internal section of micro tends to behave improperly, then still nothing bad will happen, because the built-in charge pump is no longer able to generate the burning voltage needed to write a byte into the code memory. That's the way it works in the discrete flash memory chips, so why shouldn't the microcontroller people be able to embed a similar logic to prevent the internal flash code memory of micro from being erroneously written?? My concern is based first on my own observation of "things" happening when Vcc is below 4.5 volts with RESET true, if Vreset a bit below Vcc can be considered a true RESET under those conditions. Why are you so possessed from the idea, that this micro thing will become entirely chaotic, whenever the supply falls under 4.5V?? That only a forced instantaneous collapse of supply voltage with all its disadvantages will "solve" the "problem"? As for me being possessed, maybe I am, but I'm much more disturbed by the fact that nobody has traced a "RESET" problem down to any signal sequence that's abnormal to the extent that they can tell about it and indicate why the problem was caused by a RESET fault. Engineers perform failure mode and effects analyses when things go wrong. They analyze the circuit based on theory and specified conditions, determine what effects each behavioral deviation might cause, and then attempt to show that that set of conditions exists, and, further, that that is what caused the failure. It doesn't appear that anyone has attempted to isolate or verify this "RESET" fault. I find that disappointing. That the datasheet does not contain information about such an internal section does not need to mean that something like that isn't built-in. Are you really thinking a micro is as simple constructed as the simplicity of datasheet will make you believe? The hell is going on in these beasts, and believe me, the manufacturer have found a way to prevent this damned flash code memory from being eroneously written or changed, if yes, if you only follow the recommendations of the manufacturer and keep this shitty RESET pin high during power-up and power-down.
You might have read this once or even multiple times, but you insist so intensively that ATMEL is a shitty firm, that you will not notice that they have written a plenty of brilliant application notes about this topic, wherein, yes, they recommend you to use a reset chip or circuitry, which, yes, has to guarantee that the reset pin is held high during all undervoltage situations. Not one manufacturer says that a supervisor is mandatory in order to ensure orderly operation. They hint around the notion that it might be helpful and recommend it in app-notes. I don't say that ATMEL is a "shitty" firm, to use your words, but I do not use their products under any circumstances, unless specifically directed to do so. The reason I believe that holding RESET=Vcc while Vcc decays won't stop erratic or undesired operation is because of what I've observed, and not because of any conjecture. Richard, the needed information of how to make a micro successfully work is here, but you must read it and follow the manufacturers' recommendations. I've read lots of these datasheets, even ATMEL's, and, in fact, that's why I don't use ATMEL products unless I'm forced to do so. Richard said:
Has even ONE 805x-clone manufacturer stated that you must use a supervisor in order to ensure valid reset? Yehesssss!! But I'm tired to show you the link, because 1. you won't read and believe it, and 2. the next discussion you will bring the same statement again, as if we never had discussed these things. I become tired to defend my stand-point again and again and again.. The key word here is MUST. I've seen no datasheet that clearly states that the product will not work reliably without a supervisor. I've seen app-notes that discuss them. I've seen references, in cases where the manufacturer also builds RESET IC's, but, sadly, none of theirs will work with their 805x product. Richard said:
What? The MAX1232 works at Vcc = 0 volts?. Not the MAX1232, but the whole scheme, as explained above. I'm not sure what you mean. Richard said:
Why do they all still claim that the old 10 uF cap to Vcc and external or internal 8k2 pulldown is all that's needed? No, not all do that. The datasheet of AT89S52 is free from such claims. But, I forgot, you hate ATMEL and won't ever read this datasheet. Richard said:
Are you saying that the circuit you've provided will always provide a valid reset, regardless of +5 supply behavior, and the AT89S52 will never corrupt its flash if that circuit is used? That's my best approach to solve this reset issue. Show me a better if you can and I will adopt it, immediately. Regards, Kai As time allows, I'll be preparing a testbed within which I can observe various parameters during fluctuating Vcc, various rise and fall times, etc. Then we'll have a long-term test on which to base conclusions. Until such time as I have precise observation data of purported RESET faults, though, I have nothing to test. What that means is that I'll be looking in further detail at that situation with the decaying Vcc with RESET=Vcc, and Vcc decaying below 4.5 volts, resulting in corrupted BBRAM. That will probably lead to some lively discussion. I don't hate ATMEL ... they're not worth the energy. I just don't use 'em, nor do I suggest them to my clients, thanks to the terrible treatment we got from them when we attempted to do that. Of the two ATMEL products, one CPU and one RF component we thought we were using, neither turned out to be useable. RE |
