| ??? 07/02/03 02:16 Read: times |
#49823 - Short Timing delays |
When interfacing peripherals to MCU in the memory mapped mode, certain of the bus timings are already fixed. Like for instance if I need to interface a memory chip in this mode with the 74138 handling the address decoding, I guess there is little I can do to alter the tming sequence ( for the given hardware ) in which RD# or #WR signals arrive at the memory chip in relation to the chip select and data pulses.
The query is : Suppose in a particular setup I need to delay the #WR signal by 50 nanosecond to the memory chip then what are the options ? Introducing another gate in the path may fetch this with the additional propogation delay - but at times may or may not be physically possible. I am looking for some guidelines in this respect. ( The memory chip is just an example - it could be any peripheral.) Incidentally I did a search for 'short timing delays' and landed on this good article Bus Cycles from Avocet. http://www.avocetsystems.com/company/a...buscyc.htm Thanks Raghu |



