I believe that my terminology for the gate shown in the above posting is accurate. I stated it as a "two input low level NAND".

You may recall a graphic I posted to this forum a while back......


Using text to describe the names of the gates in this figure I use:

7400 - 2 input NAND  ==   2 input low OR

7402 - 2 input NOR   ==   2 input low AND

7408 - 2 input AND   ==   2 input low NOR

7432 - 2 input OR    ==   2 input low NAND

I think everbody will agree that the names described in the first column of the above table are the generally accepted names for these gates. This is borne out by the figure below which was blatently copied from the headers of four different TI data sheets.


The names I use in the second column of the table are based upon some convention as well. The figure below shows the generic gate elements that are included in the Lattice Semiconductor ispLEVER CPLD/FPGA design package. The element names shown include a suffix number that specifies the number of low active inputs to the gate. (Note I have just shown the combinations from the Lattice library that are equivalents to those in the diagram above. They also have generic elements with one low active input and one high active input in which case the suffix number in the element name is 1.



Hope this clears things up a bit. I believe that I showed the original gate the way I intended and that it would come from part of a 74xx32 package. If you feel further discussion is needed please by all means post back here.

Michael Karas