| ??? 07/03/03 02:07 Read: times |
#49930 - RE: Short Timing delays Responding to: ???'s previous message |
Dear Mike,
Interesting. The back-n-forth between you and Erik helped to drive in the concept behind your schematic even more clearly ! And when I said in my earlier post that : "unless Mike confirms if the bubble is meant to represent 'logical inversion' or 'negative logic convention' ambiguity is bound to be there." This ambiguity is what I referred to - something that was learnt some 20 years back about having bubbles on both inputs and outputs. Raghu |



