| ??? 07/02/03 20:18 Read: times |
#49910 - RE: Short Timing delays Responding to: ???'s previous message |
Erik:
I'm not trying to stretch out the trailing edge of the -WR signal. If you go back and read both what Raghunathan said he needed and what I posted was circuit to actually shrink the low width of the -WR signal by delaying its leading edge. I even pointed out in my post the desirability to use a fast gate so as to minimize the skewing in the trailing edge of the write pulse. Too much delay there and the end of write could extend into the time when -CS from the '138 is ending. Michael Karas |



