Hallo Raghunathan,

first to Michael's drawing: It's very detailed and absolutely correct. And it goes far beyond your actual question. You wanted to know how to introduce 50nsec delay, but Michael showed you a solution which gives you this delay, but at the same time helps you to prevent damage caused by bus contention! If you have a look at bus timing specification, you will see, that 0-to-1 transition of !RD signal must not be delayed very much. The relevant parameter tRHDZ (data float after !RD) must not be violated. For 24MHz tRHDZ is 55nsec maximum (AT89C51), which means, that 55nsec after 0-to-1 transition your external memory must have floated data bus. If you now introduce more than 50nsec delay for !RD signal, and 0-to-1 transition comes more than 50nsec later, bus contention is possible, which can result in some damage.
Delay circuit Michael discussed, does not introduce the delay for 0-to-1 transition of !RD, but only for 1-to-0 transition, and so preventing your application from bus contention! Only the propagation delay of 74AC32 has to be taken into account, but this is well, well below 50nsec.
Delay of 1-to-0 transition of !RD signal, on the other hand, cannot cause any damage. !RD low pulse must only be wide enough for fullfilling timing requirements of memory.

I just wanted to focuse this point, briefly. That's the reason, why Michael gated the delay with a 2-INPUT POSTIVE-OR gate.

Now to your actual question of how to implement a 50nsec delay.
Use of propagation delay of digital gate circuitry is indeed widely used in electronics. If you choose 74HCMOS family for this job, calculation of propagation delay time is very eased, because propagation is almost identical for 0-to-1 transitions and 1-to-0 transistions.
Specifications of propagation delay time is very nicely discussed in the following application note:

http://www.fairchildsemi.com/an/AN/AN-317.pdf

Propagation delay time depends on three parameters: Supply voltage, capacitive load at output and temperature. If you do not change capactive load in your application, then only supply voltage and temperature is relevant. For a 74HC00 or 74HC04 propagation delay time varies about +-2.5%, when supply voltage changes from 4.5V to 5.5V. If you keep Vcc rather stable, by simply using normal voltage regulator, change of propagation delay time with supply voltage is almost neglectable, may be something less than +-1%.
Temperature dependency is much higher: About 0.3% per °C. So, when your ambient temperatur shows a change of +-20°C, then change of propagation delay time is about +-6%.
Combined with +-1% caused by power supply change, resulting change of propagation delay time is about +-7%.
Now, let's discuss a typical application: If we use all 6 inverters of 74HC04, then total propagation delay time is about 6 x 7nsec = 42nsec. With +-7% change it results:

Propagation delay time is: 42nsec +-3nsec

You might ask, where the missing 8nsec are (50nsec is the target, right?). If you use 74HC32, then there is an additional propagation delay time of OR-gate of about 8nsec, so, finally resulting in 50nsec. Tolerance of this additional gate has to be added, of course, and you get +-3.5nsec, totally, for 50nsec propagation delay time.

But keep in mind that this calculation was derived from typical performance, so actual performance may differ from this value. In reality, you could use a socket, so that you can change 74HC04 devices, if it drastically differs in propagation delay time.

Finally some comments to 'bubble-discussion':

If you develop such an OR-gated delay, you first make a truth table. With only two inputs, you see very fast, whether this truth table can be solved with AND, NAND, OR, NOR or EXOR gate. And you see, whether one or both input signals have to be inverted. Often, you can see directly, that truth table can be solved with the help of some NAND gates of 74HC00, e.g. In our example OR gate can be implemented by the use of 3 two-input NAND gates, or two inverters and one two-input NAND gate, or one two-input OR gate, of course. (All gates assumed to be positive logic. Also assumed, that propagation delay times are well matched to achieve 50nsec delay.)

Question arises, why Michael does not draw OR gate symbol in his drawing. One reason might be, he loves bubbles...{grin}. But more probably, he wanted to follow a certain tradition, namely to indicate, that input signals and output signals are negative logic, means are active when showing low level. This is indeed the case, because one input signal is !RD, other input signal is a delayed copy of !RD, and output, finally, is modified !RD signal. So, all three signals are negative logic. From my point of view correct name of this gate is: '2-INPUT POSTIVE-OR gate'. Equivalent name is: '2-INPUT NEGATIVE-AND gate'. 'NEGATIVE' means, that gate needs bubbles at every input and every output. And an AND gate with bubbles at every input and output is a NEGATIVE-AND gate, or a POSITIVE-OR gate.

Bye,
Kai