karas wrote:
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I stated it as a "two input low level NAND"

erik responded:
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but drew it as aa low level AND



My symbology and terminology follows the conventions I cited in the lengthy post just prior. I happen to go by the terminology that a symbol like this.....



...is a NAND. And notice I've omitted saying anything about the input characteristics in this picture. It is drawn AND with a negated output - thus NAND. In my original post I used "two input low level" to mean that I wanted 2 low active inputs. I do agree that I could have written it to say "two input low active NAND" but I have a habit with logic to use the words "level" and "active" in place of each other. Maybe that is confusing the issue here and I should have written active as opposed to level.

I follow the convention from the Lattice library, which incidently is derived from the Senario library, and is used in the schematic drawing packages for several FPGA vendors including QuickLogic and Lattice and possibly others.

Michael