The external bus timing sequences are programmable on some 8051 processor derivatives. Using one of these chips is perhaps the easiest way to acheive timing variance of the transaction sequence to/from a peripheral or memory component. I can recall that the Dallas 80C320 part is somewhat programmable. All of the Cygnal parts that sport the EMIF (external memory interface), such as the C8051F020, have very flexible programmable timing.

For some applications the programmable timing permits one to custom taylor the performance to/from peripherals on a device by device basis. Thus if you had a slow parallel EEPROM you could by default set a slower speed, but at the time you come to squirt 4K or 8K bytes of graphics data to an LCD module that has a high performance parallel interface the bus speed could be stepped up to fast mode to minimize the number of clock cycles needed to update the display.

Another way to change the transaction timing on the external bus is to change the controller oscillator frequency. Then any of the timing relationships on the bus that relate back to the oscillator will shift based on the frequency. (Note that not all timing specifications are directly proportional to the oscillator period. Certain timing specs for signals on the external bus will be propagation delay specific). If you employ an external can type oscillator with PLL it is possible to use port pins to reconfigure the oscillator to run at different speeds. For example I have seen one design that had a clock generator chip that produced a 1x or 0.5x output based upon the setting of an input pin. Software can then easily control its own execution speed with these schemes and correspondingly the timing parameters of the external bus.

Michael Karas