A hardware solution to provide a -WR pulse to a peripheral or memory chip that has its leading edge delayed can be implemented using a circuit like shown below.

In this case the timing sequence shows address only decoding via a 74xx138 type chip that produces a chip select (-CS) for a peripheral or memory chip. If the detailed timing analysis then reveals that the leading edge of this decoded -CS signal does not proceed the leading edge of the -WR signal from the microcontroller by sufficient margin to satisfy the timing requirements of the peripheral then the leading edge can be delayed through use of a two input low level NAND gate such as a 74xx32. The delay on the second pin can be generated in various ways, many of them ways I would not like to recommend. A quite good solution for the delay is to select one of the Dallas Silicon Delay Lines such as shown at this link http://www.maxim-ic.com/quick_view2.cfm?qv_pk=2604

In the diagram I also show the use of a 74AC32 type gate. This was shown only to illustrate that it may be necessary to utilize a rather fast gate so as to minimize the overall skew introduced in the trailing edge of the -WR_DLY signal due to the propagation delay of the gate. If this circuit were used in your design careful timing analysis needs to be done to ensure that the delays meet the needs of your hardware components.



Michael Karas