I would not use an R/C delay in a production product nor would I use a string of 6 inverters as Kai talked about.

Yes, Michael, but delay lines are rather expensive and current consumption can be much higher. Why not using pre-selected 74HC04 device? Go-nogo test would need only less than 10sec.
By the way, R/C delay in combination with Schmitt-trigger gate I wouldn't use, either, because an additional parameter, namely temperature dependency of threshold voltage, has to be taken into account.

I will generally analyze these cases with min values that are 1/3 the max spec. Thus if a data sheet calls out a gate prop delay of 18 nsec, but no min value, then I will use 6 nsec as the minimum.

Deviation can be even much higher. Fairchild 'specifies' minimum value of propagation delay time to about 0.4 to 0.7 of typical value. So, for a 74HC00 having 9nsec typical propagation delay time and 18nsec maximum, about 4nsec results for mimimum value.
Happily, these extremes are very seldom, and when some pre-selection is done trouble of deviation can be eliminated.
One important point: Deviation of propagation delay time decreases when capacitive load is minimized, because output impedance of gate in combination with capacitive load introduces an additional term, which is minimized when capacitive load is minimized. 50 Ohm output impedance in combination with 50pF gives time constant of 2.5nsec, so, from 9nsec typical propagation delay time this is about one third. Time constant will not contribute much to propagation delay time only, when capacitive load is minimized, which is the case in a delay line built from an inverter string.

But you are right, of course, specialized delay line chip will do the job much more reliable.

Bye,
Kai