| ??? 07/10/03 02:11 Read: times |
#50388 - RE: Short Timing delays- Dave Responding to: ???'s previous message |
Dear Dave,
Thanks for your time. But I think the solutions of introducing a Delay Line or using a chip like C8051F020 which has a SFR for External Memory Timing control WILL solve the problem. Let me explain the actual timings of a typical 80c51 from Philips with 12Mhz clock and 12clock cycles: External Memory Read : 200 nanoseconds after #ALE goes low, #RD goes low and remains low for 399.8 nanoseconds. Immediatley after #RD goes low, P0 is ready to take data in for 399.8 nanapseconds and address valid to data valid is 859.5 nanoseconds. What I am trying to do is to play around within the time frames that have been indicated in bold above and give the external chip the additional time to prepare its data. And your concern was : "could mean that the RD pulse will have gone high internally, and therfore latched the data bus contents, long before the data is valid. " The above cannot happen, if I do, what I have explained above. Raghu I think this |



