| ??? 03/02/05 15:15 Modified: 03/02/05 15:16 Read: times Msg Score: +1 +1 Good Answer/Helpful |
#88874 - stack and rest features Responding to: ???'s previous message |
hi,
Jan Waclawek said:
Adding an upper byte to stack pointer is trivial and seamless, consumes close to nil silicon area, and by no means violates the '51-ness. Having a bigger stack, high-level language compilers would have much easier life.
Jan, it is already done for some 8051-like devices. If I remember right, Dallas C400 serie has 1kB additional on-chip SRAM usable as stack/data memory. And alot of other features include 4 DPTRs, 3 serial ports, 4 Timers/Counters, IEEE 802.3 Ethernet interface with TCP/IP in ROM, 1-Wire Net controller, 16 Interrupts/3 priority levels, 9kB on-chip SRAM, 16/32-bit math coprocessor, it addresses up to 16 MB external memory etc. I think it is enough for most requirements. By the way, IMHO: I do not see a reason of this thread. Indeed, we may dream about anything but we have only that vendors produce. So think about: either you need much more and so come to select another core, or just take what they produce and make your work with it "as it is". It is my opinion, but I have no time to dream, I just select appropriate derivative and do what I need with it. Regards, Oleg |
