I get the picture.

basically the data lines will be standard except that buffers separate the data lines, and the parallel port.

My design will detect when PSEN pin is low, and when it is, it will stop the CPU clock, and enable the buffers so the parallel port's data can override the entire data bus, which then sends the data to the EEPROM. The EEPROM's WR' pin is controlled directly by the parallel port for simplicity.

I will make software that will send the correct signals to the parallel port.

Once the byte is written, then I send another signal from the parallel port, that once again enables the clock, and disable the buffers. This means that whatever arrives from the port is ignored, because the output would be high impedance.

Also, the chips providing output will also be disabled during the entire programming process, because their OE' and WE' lines are high.

At this point in time, the data bus will be logic low, because I tied each bit in the bus to ground through a resistor bus.

I bet it takes more than one clock cycle to convert the 8051's "Port 0" to outputs.

Once the chip is programmed, I will switch a jumper, so that PSEN is connected to the OE' pin on the EEPROM., the buffers (for the parallel port) will be disabled forever, and the system will run.

I have to admit, that this project is one of my biggest. In fact, right now, it is using more than 10cm, by 10cm circuit board space.